This disclosure relates generally to the field of semiconductor device fabrication, and more particularly to formation of complementary metal oxide semiconductor (CMOS) devices having interfacial oxide of different thicknesses on the same chip or substrate.
State of the art integrated circuit (IC) chips must be able to allow a wide range of on-chip voltages across devices on the chip, while increasing circuit performance and design flexibility. An increasing demand exists for providing semiconductor chips having devices, such as field effect transistors (FETs), with interfacial oxide layers of various thicknesses. Interfacial oxide thickness between the device gate and the substrate on which the device is located is a major concern in terms of reliability considerations for devices operating at different voltage levels. Device scaling trends have led to low voltage operation in devices having relatively thin interfacial oxides, such as devices that are used for memory or logic. Other applications may require a relatively thick interfacial oxide, such as driver/receiver circuitry at a chip input/output (I/O) and analog output devices. Thick interfacial oxide is necessary for high voltage devices to ensure reliability, while thin interfacial oxide is desirable for the relatively fast logic devices that use low voltages at the gate. However, the use of relatively thick interfacial oxide for lower voltage devices can cause poor device performance and significantly decrease speed.
Moreover, with the trend of to forming as many different circuits as possible on the same substrate, or chip, to achieve more functionality and/or improve performance, there are even more different possible combinations for different parts of circuits in the same chip to have different interfacial oxide thicknesses to achieve the optimized performance and reliability at the system level.
One method of forming different interfacial oxide thicknesses on the same substrate involves multiple masking, strip, and oxide formation steps. However, such an approach may significantly increase the overall manufacturing cost and degrade the reliability and yield of the manufacturing process. The interfacial oxide thickness may also be difficult to control because the thick oxide layer results from the combination of multiple oxide formation cycles.
Another method for providing multiple interfacial oxide thicknesses employs a nitrogen implant for retarding the oxidation rate on the thin interfacial oxide devices, while permitting a thicker oxide to grow where the nitrogen implant has been blocked. However, the use of nitrogen implants may cause problems. For example, implanting nitrogen at high doses may introduce beam damage in the channel region of FET devices. This damage in turn results in changes in the channel impurity distributions as well as introducing silicon defects which can degrade sub-threshold voltage leakage (off current), interfacial oxide breakdown voltage, and device reliability.